1. Field of the Invention
The present invention relates to a semiconductor memory device such as a nonvolatile semiconductor memory and a method of manufacturing a semiconductor memory device.
2. Description of the Related Art
The nonvolatile semiconductor memory is able to retain stored data without requiring electricity, and is used as a memory in a low power-consumption device such as a mobile device. Recently, an Oxide-Nitride-Oxide (ONO) structure having a silicon nitride film capable of storing electric charge and a floating gate structure having a polysilicon are widely used as the nonvolatile semiconductor memory. The ONO structure is disclosed in, for example, the Japanese Patent Application Kokai (Laid-Open) Publication No. 2002-280464 (referred to as Patent Document 1). The floating gate structure is disclosed in, for example, the Japanese Patent Application Kokai (Laid-Open) Publication No. 2002-33405 (referred to as Patent Document 2).and the Japanese Patent Application Kokai (Laid-Open) Publication No. 10-189917 (referred to as Patent Document 3).
In the nonvolatile semiconductor memory having the floating gate structure disclosed in Patent Document 2, the floating gates and the control gates are laminated via the silicon oxide layers on the semiconductor substrate, on which impurity diffusion regions serving as bit lines are formed.
In the nonvolatile semiconductor memory having the floating gate structure disclosed in Patent Document 3, the grooves are formed on the semiconductor substrate, and the floating gates are formed in the grooves. Impurity ions are implanted into parts of the semiconductor substrate, in which the floating gates are not formed in the grooves, so that the impurity diffusion regions serving as bit lines are formed.
However, in the nonvolatile semiconductor memory disclosed in Patent Document 2, the floating gate and the control gate are formed on the semiconductor substrate, and therefore the height of the memory cell region, in which the gates are formed, becomes higher than the surrounding transistor regions. If the height of the memory cell region increases, the difference in height between the memory cell region and the transistor region increases, with the result that it becomes difficult to obtain finer cells.
In the nonvolatile semiconductor memory disclosed in Patent Document 3, the floating gate is buried in the groove, and therefore the difference in height between the memory cell region and the transistor region can be reduced. However, impurity ions are implanted into a bottom surface of the groove from right above, and implanted into a side surface of the groove in an oblique direction. Therefore, if the width of the groove is reduced for obtaining finer cells, the impurity ions are blocked by the surface to the semiconductor substrate. Therefore, the impurity ions are not implanted into a part of the side surface close to the bottom surface. As a result, the resistance of the impurity diffusion region serving as a bit line increases, so that it becomes difficult to obtain finer cells.